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[Other resource] very-good-ok-ref-ddr-sdram-verilog

Description: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Platform: | Size: 895594 | Author: 姚明 | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
Platform: | Size: 131072 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram控制器 这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements.
Platform: | Size: 3072 | Author: 林博 | Hits:

[VHDL-FPGA-Verilog] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347136 | Author: Hubert | Hits:

[VHDL-FPGA-Verilog] very-good-ok-ref-ddr-sdram-verilog

Description: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Platform: | Size: 894976 | Author: 姚明 | Hits:

[Software Engineering] DDR_SDRAM_controller_verilog

Description: DDR SRAM控制器的verilog完整设计文档（包含有完整的verilog源代码），-DDR SRAM controller complete Verilog design documents (including a complete Verilog source code),
Platform: | Size: 475136 | Author: lipengfei | Hits:

[VHDL-FPGA-Verilog] zbt_rd_vhdl_str_v1.0.0

Description: ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules
Platform: | Size: 1688576 | Author: li ji wei | Hits:

[Other] 128Mb_ddr

Description: 128Mb DDR verilog源程序-128Mb DDR verilog source code
Platform: | Size: 23552 | Author: tiantian | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_verilog

Description: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
Platform: | Size: 752640 | Author: 宋珂 | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
Platform: | Size: 678912 | Author: liujie | Hits:

[VHDL-FPGA-Verilog] c_xapp260

Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Platform: | Size: 1123328 | Author: 陈阳 | Hits:

[Other] rtl

Description: ddr controller in verilog-ddr controller in verilog...............
Platform: | Size: 69632 | Author: guanchuanjian | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 基于FPGA的ddr控制器的设计与实现，verilog，ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
Platform: | Size: 179200 | Author: 洪依 | Hits:

[Windows Develop] DDR-SDRAM

Description: ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
Platform: | Size: 903168 | Author: 何海山 | Hits:

[VHDL-FPGA-Verilog] ddr_verilog

Description: DDR控制器的VERILOG代码；状态机；读写；刷新等操作-ddr controller,verilog
Platform: | Size: 677888 | Author: 雷恒伟 | Hits:

[VHDL-FPGA-Verilog] dab1814114c3

Description: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 880640 | Author: 李志偉 | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM-controller-verilog-code

Description: DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM controller verilog code and documentation
Platform: | Size: 488448 | Author: 一样 | Hits:

[Embeded-SCM Develop] DDR_MO

Description: 使用verilog语言实现简单的DDR SDRAM控制器(Using Verilog language to achieve a simple DDR SDRAM controller)
Platform: | Size: 1101824 | Author: 搬砖123 | Hits:
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